The present invention relates to a substrate with a test circuit for a thin film transistor liquid crystal display (TFT-LCD).
As the technology for manufacturing a thin film transistor liquid crystal display (TFT-LCD) is gradually perfected and the cost thereof is gradually reduced, the TFT-LCD has been used widely.
A current method for manufacturing a TFT-LCD may comprise the steps: forming some individual TFT pixel array regions on one large substrate with each of the TFT pixel array regions corresponding to an individual panel. In order to perform the signal detection on the TFT pixel array regions formed on the substrate, test circuits for inputting test signals are formed on the substrate together with the TFT pixel array regions. The test circuits are formed around each of the TFT pixel array regions on the substrate. Then, occurrence of electric defects in each of the TFT pixel array regions may be detected by inputting the test signals via test inputs terminal of the test circuits. After the test, liquid crystal is applied on the substrate on which the TFT pixel array regions have been formed. A color filter substrate is put above and assembled to the substrate having the TFT pixel array regions and a large LCD panel is formed. Finally, the large LCD panel is cutting and at the same time the test circuits around each of the pixel array regions are also removed by cutting, and thus individual panels are obtained. FIG. 1 is a schematic view illustrating the structure of the large substrate with test circuits, and as shown in FIG. 1, during the process of forming the TFT pixel array regions and test circuits in the peripheral regions, exposure processes are performed based on two individual panels as an exposure unit. In FIG. 1, twelve individual panels, that is, 1st panel to 12th panel, are arranged on the substrate in an array, and thus, the exposure processes are performed six times because there are six exposure units, and each of the six exposure units is showed as a region surrounded by the dashed lines in FIG. 1. Because a same mask is used for each of the exposure units, the resultant pattern structures are identical among the exposures. Furthermore, the corresponding test circuits are also formed based on the exposure units. The test signal lines for each of the individual panels comprise a data-line-test line, a gate-line-test line and a common-electrode-line-test line, and each of the test signal lines has two test input terminal positioned respectively at an outer edge and a central region of the substrate.
FIG. 2 is a schematic view illustrating a structure for detecting an electric defect occurring in the substrate shown in FIG. 1. As shown in FIG. 2, when a test signal is loaded to the central region, a beam 51 having probes 52 is provided to a device probe frame 5, which is used to positioned the probes 52 such that the test signal can be loaded to the individual panels. The probes 52 contact corresponding test input terminals. Because a distance between a sensor for detecting the electric defect and the panel is only about 15 μm, when the test is performed, it is necessary to raise the sensor one time to go around the beam 51 when passing the beam 51. Thus, this increases the time used for the test and disadvantageously influence the test efficiency. Therefore, when the test on the electric defect is performed, the test input terminal at the central area is not used and only the test input terminal at the outer edge of the substrate is used.
Because only the test input terminals positioned at the outer edge of the substrate are used and the input resistances between the test input terminals at the outer edge of the substrate and the test signal lines corresponding to each of the individual panels are different, the voltage drops are different during the test signal transmission, and thus, the test signals actually loaded to the individual panels are different and the ability of the test circuits to detect the electric defect of each of the individual panels are different.